Low power consumption of current mirrored footed domino comparator using lector technique

Abstract

This paper presents plan of a leakage-tolerant design technique for high fan-in dynamic circuits is presented. Diode Footed Domino (DFD) comparator is utilizing footer transistor in diode configuration to reduce sub threshold leakage. The power is not diminished by the use of comparator. Dynamic comparator is aimed by the diode footed domino method to exhibit the effectiveness of the wished-for structure in enlightening leakagetolerant. A method using lector technique is proposed to reduce power. Lector is a technique to reduce the problem of leakage in CMOS circuits, it includes a n-type and p-type leakage controlled transistors (LCTs), between supply to ground which are self-controlled and proposals the additional resistance, which will diminish the difficult of leakage current in the CMOS circuits. LCT‘s is self-controlled transistors.