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Abstract
This paper presents a high-throughput and low-complexity BCH decoder for NAND flash memory applications, which is developed to achieve a high data rate demanded in the recent serial interface standards. To reduce the decoding latency, a data sequence read from a flash memory channel is re-encoded by using the encoder that is idle at that time. In addition, several optimizing methods are proposed to relax the hardware complexity of a massive-parallel BCH decoder and increase the operating frequency. In a 130-nm CMOS process, a (8640, 8192, 32) BCH decoder designed as a prototype provides a decoding throughput of 6.4 Gb/s while occupying an area of 0.85 mm2
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How to Cite
V.Marimuthu, D.Ramya, R.K.Uma Maheswari, & S.Arunodhaya. (2018). A survey of solid-state drives using BCH decoding architecture . International Journal of Intellectual Advancements and Research in Engineering Computations, 6(1), 174–179. Retrieved from https://ijiarec.com/ijiarec/article/view/431