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Abstract

A new binary counter design is proposed. It uses 3-bit stacking circuits, which group all of the “1” bits together, followed by a novel symmetric method to combine pairs of 3-bit stacks into 6-bit stacks. The bit stacks are then converted in to binary counts, producing 6:3 counter circuits without xor gates on the critical path. The eliminated xor gates results in faster designs with efficient power and area utilization. In the proposed work “and, or, xor” gates are replaced by 4:1 multiplier to design the 6:3 counter. The proposed counters in existing counter-based on Wallace tree multiplier architectures reduces latency and power consumption for 64 bit multipliers.

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How to Cite
V.Marimuthu, & P.Sukumar. (2019). Implementation of Fast Binary Counters using Symmetric Stacking . International Journal of Intellectual Advancements and Research in Engineering Computations, 7(1), 1245–1249. Retrieved from https://ijiarec.com/ijiarec/article/view/1115