Implementation of low power and fast full adder by using new XOR and XNOR gates

Abstract

Many existing XOR-XNOR cells suffer from non-full-swing outputs, high power consumption and low speed issues. In this paper, a new fast, full-swing and low-power XOR XNOR cell, is presented. Each of the proposed circuits has its own merits in terms of speed, power consumption, power delay product (PDP), driving ability, and so on. To investigate the performance of the proposed designs, extensive TSPICE and TANNER simulations are for XOR/XNOR and simultaneous XOR–XNOR functions are proposed. The proposed circuits are highly optimized in terms of the power consumption and delay, which are due to low output capacitance and low short-circuit power dissipation. The full swing XOR/XNOR and non-full swing XOR/XNOR gate circuits are used to propose new Full Adder design in order to optimize power, delay and PDP (Power delay product) of the low power circuits. The simulation results, based on the 65-nm CMOS process technology model, indicate that the proposed designs have superior speed and power against other FA designs performed.