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Design of Internet of Things (IoT) is an emerging technique this is widely used to design energy-efficient and secure IoT devices. For example, IoT devices such as Radio Frequency Identification (RFID) tags and Wireless Sensor network Nodes (WSN) employ AES cryptographic module that are vulnerable to Differential Power Analysis (DPA) attacks. As the technology scaled down, leakage power in the cryptographic device increases, which increases their vulnerability to DPA attack but occupation of the device area minimized by the use of FinFET technology. This paper presents a novel FinFET based Secure Adiabatic Logic (FinSAL) that is energy-efficient and has more DPA-immunity. The proposed adiabatic FinSAL is used to construct that logic gates such as buffers, XOR, and NAND. Hence the logic gates based on adiabatic FinSAL are used to design a Positive Polarity Reed Muller (PPRM) architecture based S-box circuit. Then the designed circuit has been simulated with SPICE simulations at 12 MHz and it will reflects that adiabatic FinSAL (20nm FinFET technology) S-box circuit saves power up to 85% of energy per cycle as compared to the conventional S-box circuit implemented using FinFET (20nm FinFET technology). We proved that the FinSAL S-box circuit is highly resistant to a DPA attack through a developed DPA attack flow applicable to SPICE simulations. Further, the impacts of FinSAL on hardware security at different technology nodes of FinFETs (7nm, 10nm, 14nm, 16nm) are evaluated. From the simulation results, FinSAL gates at 14nm FinFET offer superior security with optimum power consumption, therefore is the best candidate to design low-power secure IoT devices.

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T.M.Sathish Kumar, R.Saraswathi, & S.Ragavi. (2019). Design of energy-efficient IOT devices using Finfet based secure adiabatic logic . International Journal of Intellectual Advancements and Research in Engineering Computations, 7(1), 1511–1519. Retrieved from