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Speed and Area are the important parameters in various designing systems. Low power design is essential to extend the operating time of integrated circuits (ICs) additionally on reduce the packaging and cooling costs. The Phase locked loop (PLL) is an efficient method employed in frequency synthesis. Because the scale of integration keeps growing, VLSI chip is employed to implement the signal processing systems, which was more and more complex. These signal processing applications consume impressive amount of energy. The tradeoff between performance and area remain to be the two major design factors, high power consumption is critical in today’s VLSI system design. In this paper CMOS VLSI dynamic logic is employed to induce high speed, less area and reduced power of the PLL system. A dynamic logic based CMOS is proposed to design the phase detector, Voltage Controlled Oscillator and loop low pass filter (LPF). The CMOS dynamic logic is the High speed logic in all the CMOS logic families. The DSCH3 tool is employed in the design of logical circuits and micro wind 3.1 tool using 90nm CMOS technology is employed to measure the parametric analysis. The bandwidth of loop filter is the speed of the transition time between synthesized frequencies. In the dynamic CMOS logic PLL, the speed is improved to 7.25GHZ and area is reduced to 204.2 µm².

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K. Raguvaran., M.E, Mohamed Marzook S, Priyadharsini M, Ranjith P, & Shapna P. (2021). Design and analysis of area efficient, high speed PLL using 90nm CMOS technology. International Journal of Intellectual Advancements and Research in Engineering Computations, 9(2), 18–24. Retrieved from