Design of an optimized multiplier based on approximation logic

Abstract

Approximate computation decreases the design complexity of error rebounding applications. This paper deals with the approximation process for optimizing power, area and delay. The partial products of multiplication are altered based on their probability and approximated. Due to the use of probability in computation, complexity of partial product is reduced. The proposed two approximate designs are applied to 4-bit multiplier. Multiplier uses different adders like Ripple Carry Adder (RCA), and Carry Look Ahead adder (CLA). They have better precision when compared to the existing method. For the two approximate design power, area and delay constraints are compared for the multiplier with and without approximation. Multiplier designed with two approximate designs consumes low power when compared to the existing method. The proposed Multiplier 1 saves 45% & 55% of power than the existing and exact multiplier. VHDL coding is computed and the synthesis results are obtained by the Model Sim software. Power consumption, Delay and Logic Utilization are estimated using the Spartan 3E Xilinx kit.