A HIGH SPEED LOW POWER CAM AND TCAM WITH A PARITY BIT AND POWER GATED ML SENSING

Abstract

Content Addressable Memory (CAM) offers high-speed search function in a single clock cycle. Due to its parallel match-line comparison, CAM is power-hungry. Thus, robust, high-speed and sense amplifiers are highly sought-after in CAM In this paper, we introduce a parity bit that leads to 39% sensing delay reduction at a cost of less than 1% area and power overhead. We propose an effective gated-power technique to reduce the peak and average power consumption and enhance the robustness of the design against process variations. A feedback loop is employed to auto-turn off the power supply to the comparison elements and hence reduce the average power consumption by 64%. The proposed design can work at a supply voltage down to 0.5 V.A CAM is designed such that the user supplies a data word and the CAM searches its entire memory to see if that data word is stored anywhere in it. If the data word is found, the CAM returns a list of one or more storage addresses where the word was found and in some architectures, it also returns the data word, or other associated pieces of data. Thus, a CAM is the hardware embodiment of what in software terms would be called an associative array. The extra circuitry also increases power searching speed cannot be accomplished using a less costly method.