K. Raguvaran., M.E, Mohamed Marzook S, Priyadharsini M, Ranjith P, Shapna P. Design and analysis of area efficient, high speed PLL using 90nm CMOS technology. IJIAREC [Internet]. 2021Apr.22 [cited 2024Apr.26];9(2):18-24. Available from: https://ijiarec.com/ijiarec/article/view/20