K. Raguvaran., M.E, Mohamed Marzook S, Priyadharsini M, Ranjith P and Shapna P (2021) “Design and analysis of area efficient, high speed PLL using 90nm CMOS technology”, International journal of intellectual advancements and research in engineering computations, 9(2), pp. 18–24. Available at: https://ijiarec.com/ijiarec/article/view/20 (Accessed: 9May2021).