K. RAGUVARAN., M.E; MOHAMED MARZOOK S; PRIYADHARSINI M; RANJITH P; SHAPNA P. Design and analysis of area efficient, high speed PLL using 90nm CMOS technology. International journal of intellectual advancements and research in engineering computations, [S. l.], v. 9, n. 2, p. 18–24, 2021. Disponível em: https://ijiarec.com/ijiarec/article/view/20. Acesso em: 20 oct. 2021.