K. Raguvaran., M.E, Mohamed Marzook S, Priyadharsini M, Ranjith P, & Shapna P. (2021). Design and analysis of area efficient, high speed PLL using 90nm CMOS technology. International Journal of Intellectual Advancements and Research in Engineering Computations, 9(2), 18–24. https://doi.org/10.61096/ijiarec.v9.iss2.2021.18-24