Articles

  1. SUPERPIXEL CLASSIFICATION BASED OPTIC DISC AND OPTIC CUP SEGMENTATION FOR GLAUCOMA SCREENINGDownload Article

    *1Ms.D.Sakila, *2Ms.G.Sasikala,M.E.,

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    Glaucoma is a chronic eye disease that leads to vision loss. As it cannot be cured, detecting the disease in time is important. Current tests using intraocular pressure (IOP) are not sensitive enough for population based glaucoma screening. Optic nerve head assessment in retinal fundus images is both more promising and superior. This paper proposes optic disc and optic cup segmentation using super pixel classification for glaucoma screening. In optic disc segmentation, histograms, and center surround statistics are used to classify each super pixel as disc or non-disc. A self-assessment reliability score is computed to evaluate the quality of the automated optic disc segmentation. For optic cup segmentation, in addition to the histograms and center surround statistics, the location information is also included into the feature space to boost the performance. The proposed segmentation methods have been evaluated in a database of 650 images with optic disc and optic cup boundaries manually marked by trained professionals. Experimental results show an average overlapping error of 9.5% and 24.1% in optic disc and optic cup segmentation, respectively. The results also show an increase in overlapping error as the reliability score is reduced, which justifies the effectiveness of the self-assessment. The segmented optic disc and optic cup are then used to compute the cup to disc ratio for glaucoma screening. Our proposed method achieves areas under curve of 0.800 and 0.822 in two data sets, which is higher than other methods. The methods can be used for segmentation and glaucoma screening. The self-assessment will be used as an indicator of cases with large errors and enhance the clinical deployment of the automatic segmentation and screening.. Index terms: Intraocular pressure, Optic disc, Segmentation, Histograms, Glaucoma screening.

  2. A HIGH SPEED LOW POWER CAM AND TCAM WITH A PARITY BIT AND POWER GATED ML SENSINGDownload Article

    *1Mr.P.Karthikeyan, *2Mr.K. Vinothkumar,M.E.,

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    Content Addressable Memory (CAM) offers high-speed search function in a single clock cycle. Due to its parallel match-line comparison, CAM is power-hungry. Thus, robust, high-speed and sense amplifiers are highly sought-after in CAM In this paper, we introduce a parity bit that leads to 39% sensing delay reduction at a cost of less than 1% area and power overhead. We propose an effective gated-power technique to reduce the peak and average power consumption and enhance the robustness of the design against process variations. A feedback loop is employed to auto-turn off the power supply to the comparison elements and hence reduce the average power consumption by 64%. The proposed design can work at a supply voltage down to 0.5 V.A CAM is designed such that the user supplies a data word and the CAM searches its entire memory to see if that data word is stored anywhere in it. If the data word is found, the CAM returns a list of one or more storage addresses where the word was found and in some architectures, it also returns the data word, or other associated pieces of data. Thus, a CAM is the hardware embodiment of what in software terms would be called an associative array. The extra circuitry also increases power searching speed cannot be accomplished using a less costly method. Index terms: CAM, Amplifiers, Loop, Architectures.

  3. DEVELOPMENT OF DC SOURCE BASED SYSTEM GENERATOR USING SPWM FOR HIGH SWITCHING FREQUENCY DC/AC INVERTERSDownload Article

    *1Mr.V.Gopi, *2Ms.M.Gomathi,M.E.,

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    The digital implementations of Sinusoidal Pulse Width Modulation (SPWM) generators have dominated over their counterparts based on analog circuits. In this paper, an FPGA- based SPWM generator is presented, which is capable to operate at switching frequencies up to 1 MHz (requiring FPGA operation at 100–160 MHz), thus it is capable to support the high switching frequency requirements of modern single-phase dc/ac power converters. The proposed design occupies a small fraction of a medium-sized FPGA and, thus, can be incorporated in larger designs. The post layout simulation and experimental results confirm that compared to the past-proposed SPWM generation designs, the SPWM generator presented in this paper exhibits much faster switching frequency, lower power consumption, and higher accuracy of generating the desired SPWM waveform. The digital SPWM generator implementations have dominated over their counterparts based on analog circuits, since they offer higher noise immunity and less susceptibility to voltage and temperature variations typically , microcontrollers, Digital Signal Processors (DSPs) or Field Programmable Gate Arrays (FPGAs) are used for the implementation of the SPWM generation unit and the execution of dc/ac inverter control algorithms. Index terms: APWM, FPGA, DSP, SPWM.

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